Q-MPW · Shared wafer
A slot on a superconducting wafer, every quarter.
Put your designs on our shared wafer, on a fixed schedule, without paying for a full run. For prototypes, early-stage devices and academic research.
Q-MPW Technical & Operational Guide v1.0 · PDF, 734 kB
The round in progress
Q4'26, stage by stage
- 01Submissions28 Sept – 21 Oct 2026
- 02Design review21 Oct – 9 Nov 2026Today · 30 Oct
- 03Preview and lockBefore fabrication
- 04Fabrication10 Nov – 11 Dec 2026
- 05DeliveryMid-December 2026
Q-MPW · Q4'26 · Design review
Next round opens 11 January 2027.
Next round · Q1'27
- Submissions close
- 12 Feb 2027
- Chips delivered
- Mid-April 2027
- Blocks
- Open from 11 Jan
Q-MPW · Q4'26 · Fabrication
Next round opens 11 January 2027.
Next round · Q1'27
- Submissions close
- 12 Feb 2027
- Chips delivered
- Mid-April 2027
- Blocks
- Open from 11 Jan
Q-MPW · Q4'26 · Dicing and shipping
Next round opens 11 January 2027.
Next round · Q1'27
- Submissions close
- 12 Feb 2027
- Chips delivered
- Mid-April 2027
- Blocks
- Open from 11 Jan
Q-MPW · Q4'26 · Delivered
Next round opens 11 January 2027.
Next round · Q1'27
- Submissions close
- 12 Feb 2027
- Chips delivered
- Mid-April 2027
- Blocks
- Open from 11 Jan
Q-MPW · Q1'27 · Submissions open
Next shared wafer closes 12 February 2027.
33 days left to submit.
This round · Q1'27
- Submissions close
- 12 Feb 2027
- Chips delivered
- Mid-April 2027
- Blocks booked
- 2 of 6
Q-MPW · Q1'27 · Design review
Next round opens 12 April 2027.
Next round · Q2'27
- Submissions close
- With the round
- Chips delivered
- With the round
- Blocks
- Open from 12 Apr
Q-MPW · Q1'27 · Fabrication
Next round opens 12 April 2027.
Next round · Q2'27
- Submissions close
- With the round
- Chips delivered
- With the round
- Blocks
- Open from 12 Apr
Q-MPW · Q1'27 · Dicing and shipping
Next round opens 12 April 2027.
Next round · Q2'27
- Submissions close
- With the round
- Chips delivered
- With the round
- Blocks
- Open from 12 Apr
Q-MPW · Q2'27 · Submissions open
Submissions are open.
This round · Q2'27
- Submissions close
- With the round
- Chips delivered
- With the round
- Blocks booked
- 0 of 6
PDF, 734 kB · Q-MPW Technical & Operational Guide v1.0
The process
One qualified process, published upfront
- Ground plane
- 300 nm aluminium on 500 µm high-resistivity silicon
- Junctions
- Manhattan-style Josephson junctions and air bridges
- Demonstrated
- Transmon T1 up to 250 µs; CPW resonator Qi up to ~1M
Design with these variations in mind:
Junction resistance, across the wafer
±20%
Q-MPW Technical Guide, Feb 2026
Junction resistance, within a block
±10%
Q-MPW Technical Guide, Feb 2026
What you get
Your share of the wafer
- The wafer is divided into 20 × 30 mm blocks, each with six 10 × 10 mm chip slots.
- You get blocks according to your tier; the smallest, Starter, is one block.
- Submit up to two designs per round, up to 10 × 10 mm each.
Every participant receives
- MapA placement map of your chips on the wafer
- ChipsYour fabricated chips
- JJ dataJunction-resistance variation data
- ReportA delivery report on fabrication and dicing
Blocks · chip slots · price
Tiers
| Tier | Blocks | Chip slots | Designs | Price |
|---|---|---|---|---|
| Starter | 1 | 6 | Up to two | from €9,800 |
| Standard | 2 | 12 | Up to two | from €17,500 |
| Extended | 3 | 18 | Up to two | from €24,500 |
How a round works
Six steps, the same every round
Apply and sign the NDA.
Submit.
GDSII on our template, named
Participant_Design_vX.Y.gds, zipped with a README, by email.Design review.
Automated and manual design-rule check. If something fails, you get a report and a chance to resubmit.
Preview.
You see your own chips on the wafer and confirm. Then the layout is locked.
Fabrication.
In the Chalmers cleanroom, on the published process.
Delivery.
Chips arrive with a protective resist layer and a delivery report.
In 2026, rounds ran 8–10 weeks from submission deadline to delivery.
Design rules at a glance
Before you draw
The full layer table and rules are in the Technical Guide. The KLayout template is provided to participants.
| Feature | Rule | Limit |
|---|---|---|
| Ground-plane etch | Minimum linewidth and spacing | ≥ 3 µm |
| Air bridges | Feet | ≥ 10 µm |
| Distance from etched metal | ≥ 2 µm | |
| Span | ≤ 75 µm | |
| Flux holes | Distance from CPW | ≥ 10 µm |
| Never in a waveguide, not in isolated metal islands | ||
| Junctions | Mark each location with the placeholder from the template | 10 × 10 µm |
Your design stays yours
We sign an NDA before you send a single file. Only your team and our foundry see your design. Wafer previews show your chips and nothing else, and design data is handled on a need-to-know basis.
Shipping and export control
Our quantum devices are EU dual-use items (category 3A001). Every order needs a signed End-User Statement before shipping. Within the EU, and to Australia, Canada, Iceland, Japan, Liechtenstein, New Zealand, Norway, Switzerland, the UK and the US, no individual licence is needed. Anywhere else needs an export licence, which adds time, so tell us your destination early and we'll start the paperwork with you.
FAQ
Questions before you submit
Can I submit more than one design?
Yes, up to two per round, each in its own GDS file. On a single-block Starter allocation we recommend one design.
What happens if I miss the deadline?
It may be moved to the next round.
How do I clean the chips?
Acetone for 10 minutes at room temperature, rinse with IPA, dry with nitrogen. Don't use an ultrasonic bath — it can damage air bridges.
Can I get process-monitoring data?
Test structures are on every wafer for process monitoring; ask and we'll share the data.
What if I need my own process or wafer layout?
That's a full wafer run. Foundry →
Hear when the next round opens.
The full layer table and rules are in the Technical Guide.