Foundry · Process and design rules

Our superconducting process, in detail.

For the engineer comparing foundries: materials and stack, junctions, integration and packaging, design rules, measured performance and downloads.

Materials and stack

The stack, layer by layer

300 nm aluminium ground plane on 500 µm high-resistivity silicon.

  • 300 nm aluminium ground plane

  • 500 µm high-resistivity silicon

  • Manhattan-style Josephson junctions

  • Air bridges

  1. Aluminium ground plane300 nm
  2. Coplanar-waveguide centre conductor, etched into the ground plane
  3. Air bridge
  4. Al/AlOx/Al Josephson junction (overlap, Manhattan-style)
  5. AlOx tunnel barrier
  6. High-resistivity silicon500 µm

Cross-section · thicknesses not to scale

Junctions

Josephson junctions

Al/AlOx/Al junctions, Manhattan-style or Dolan-bridge. Design with these variations in mind.

Manhattan junction · top view
PhotoSEM · Manhattan junction · with scale bar
  • 1–40 kΩ

    Junction resistance range

    Foundry page and brochures, 2025

  • ±10%

    Junction size precision, with >90% yield across a 4-⁠inch wafer

    Full wafer runs

  • ±20%

    Junction resistance variation across the wafer

    Q-MPW Technical Guide, Feb 2026

  • ±10%

    Junction resistance variation within a block

    Q-MPW Technical Guide, Feb 2026

Integration and packaging

From planar chip to packaged device

Air bridges, under-bump metallisation, flip-chip.

  • Air bridges

    Part of the qualified Q-MPW process. Placement rules are under design rules below.

  • Under-bump metallisation and flip-chip

    For 3D-integrated chips. First flip-chip integrated devices delivered October 2025.

  • Packaging

    Our Qubit-in-a-Box packages show what we can package: the SMA case (gold-plated oxygen-free copper, 2 female SMA connectors) and Box20 (20 radial SMPM connectors).

  1. Box20 · Gold-plated OFHC copper
  2. 20 × Radial SMPM
Box20, the 20-port package of QiB1 and QiB2 · drawing, not to scale

Design rules summary

Before you draw

Key rules for the Q-MPW process. The full layer table and rules are in the Technical Guide.

Design rules at a glance

Technical Guide v1.0 §4
Ground-plane etch: linewidth and spacing
≥ 3 µm
Air-bridge feet
≥ 10 µm
Air-bridge clearance from etched metal
≥ 2 µm
Air-bridge span
≤ 75 µm
Flux holes: distance from CPW
≥ 10 µmNever in a waveguide, not in isolated metal islands
Junction placeholder
10 × 10 µmMark each junction location with it, from the template

Measured performance

Measured on our own devices

Measured data, datasheets and publications are on the Evidence page, each with its source and date.

See the measured data
  • 256 µs

    best measured qubit T1 (QiB0 datasheet)

    QiB0, datasheet v2.0, Oct 2025

  • 90–130 µs

    average T1, QiB0

    datasheet v2.0, Oct 2025

  • ≳1M

    resonator Qi at single-photon power

    QiB0/QiB2 datasheets

  • 250 µs

    T1 demonstrated on the Q-MPW process (Technical Guide)

    Q-MPW Technical Guide v1.0

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